Tim

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116 reputation
2
bio website stackoverflow.com/users/…
location San Jose, CA
age 27
visits member for 1 year, 1 month
seen Feb 28 at 20:28
stats profile views 5

Professional ASIC engineer with experience in RTL design, Verilog, synthesis, power, and timing issues on billion+ gate ICs.

Other hobbies include:

  • Computer Graphics
  • Android Programming
  • C++ Programming

Personal released projects:

Portfolio Map-----------Electron Flux


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